A semiconductor memory device such as a DRAM consists of a memory cell array where a plurality of memory cells are regularly arranged as a two-dimensional array, and a peripheral circuit for controlling the memory cells. Each memory cell is selected by selecting both a column signal line called a word line and a row signal line called a bit line.
Further, the DRAM device has a row decoder and a column decoder, each having a plurality of input and output terminals and a sense amplifier connected to each bit line, for amplifying a signal read from the memory cell. Here, with the high capacity and high integration of DRAM devices, a folded bit line type sense amplifier is used between a pair of bit lines BL and BL to amplify the potential difference between these two bit lines. When using such a sense amplifier, word lines equally intersect a pair of bit lines. The word lines may be arranged on top of the active region and opposite the high level bit line, or arranged on top of the field region and opposite the low level bit line. With this type of layout, the area of a unit cell may become 8F.sup.2, where F is a design rule.
In the meanwhile, with the higher integration of the DRAM device, reduction in the area of a unit cell has been demanded. However, it becomes more difficult to reduce the design rule of a unit cell due to the limit of photolithography processes and the deterioration of electric characteristics of elements. Hence, attempts have been made to reduce the area of a unit cell with the same design rule by changing the layout of a cell or the sensing method. A representative example of these attempts is an open bit line structure where a reference bit line is fixed to the edge of the cell block without being paired with a signal bit line. This can reduce the area of a unit cell down to 6F.sup.2, but has a problem of decreasing the sensing margin due to an increase in noise.
Recently, a structure where elements are arranged at both sides of an SOI substrate is being widely used to reduce the area of a unit cell. The SOI technique isolates elements from one another by forming the active elements in each silicon island on an insulating substrate. Thus, the SOI structure can provide higher integration and a reduction of processing steps, as compared to the bulk silicon structure. The active elements formed on the SOI substrate are called SOI elements. An SOI element can achieve high operating speed and low power consumption because of a reduction in parasitic capacitance.
A description of a conventional DRAM device having an SOI structure which can maximize the cell size by burying a capacitor under the silicon layer is disclosed in U.S. Pat. No. 5,102,819. This device will now be described with respect to FIGS. 1-2.
FIG. 1 shows a cell layout in a conventional DRAM device using an SOI structure. In the figure, reference numeral 20 (region shown in dotted line) denotes a unit cell consisting of an access transistor and an information storage capacitor. Reference numeral 10 denotes a storage node of the capacitor, reference numeral 5 denotes a semiconductor layer provided as an active region, reference numeral 8 denotes a storage node contact for connecting the source region of the transistor to the storage node of the capacitor, reference numeral 15 denotes a bit line contact for connecting the drain region of the transistor to the bit line, reference numeral 12 denotes a word line provided as a gate of the transistor and reference numeral "F" denotes a design rule.
FIG. 2 is a cross sectional view, taken along line 2-2' of FIG. 1. Referring to FIG. 2, a conventional DRAM cell has a semiconductor substrate 1, a second polysilicon layer 2 for the plate electrode of the capacitor formed on top of the semiconductor substrate 1, a first insulating layer 3 formed on the surface of the plate electrode 2, a recess 4 formed by etching the first insulating layer 3, and a semiconductor layer 5 formed in the recess 4. The semiconductor substrate 1, the second polysilicon layer 2, the first insulating layer 3 and the semiconductor layer 5 constitute the SOI structure. The semiconductor layer 5 is formed of a separate semiconductor substrate different from the semiconductor substrate 1.
Source/drain regions 7 and 6 of the access transistor are formed in the semiconductor layer 5. The drain region 6 is connected to the bit line 16 via a bit line contact 15 formed at the second insulating layer 14, and the source region 7 is connected to a storage node 10 of the capacitor via a storage node contact 8 formed at the first insulating layer 3. Here, reference numeral 12 denotes a gate oxide film and reference numeral 13 denotes a gate.
Each capacitor is formed at the lower portion of a corresponding access transistor. That is, the storage node 10 composed of the first polysilicon layer is formed at the lower portion of the source region 7 and is connected to the source region 7 via the storage node contact 8. A dielectric layer 11 of the capacitor is formed between the storage node 10 and the second polysilicon layer 2. Thus, the semiconductor substrate 1, the second polysilicon layer 2, the dielectric layer 11 and the storage node 10 constitute the information storage capacitor. The semiconductor substrate 1 and the second polysilicon layer 2 serve as a plate electrode of the capacitor.
In the event that a folded bit lines type sense amplifier structure is applied to such conventional DRAM devices, the word line 12 will equally intersect a pair of bit lines, will be placed on the active region 5 in the high level bit line, and will be placed on the field region 18 in the low level bit line. In addition, the bit line 16 is extended over the second insulating layer 14 in the same direction as the active region 5. Here, since a single layer bit line structure is used, a pair of bit lines of a folded bit line structure are arranged to be adjacent and at an identical height (i.e., height corresponding to the thickness of the second insulating layer 14). Therefore, to properly amplify the potential difference between these two bit lines, a sufficient distance "a" should be maintained between adjacent active regions 5 as shown in FIG. 1, and the area of a unit cell (reference numeral 20 in FIG. 1) of a conventional DRAM device with this structure becomes 8F.sup.2.